1. Technical Field
The depicted illustrative embodiment relates to superscalar data processing systems, and in particular to concurrent processing of a particular type of instructions in a superscalar data processing system. Still more particularly, the depicted illustrative embodiment relates to establishing an array within which multiple statuses of a plurality physical registers are stored during a single clock cycle permitting concurrent processing of a plurality of instructions of a particular type.
2. Description of the Related Art
A superscalar data processing system is a data processing system which includes a microprocessor architecture which is capable of executing multiple instructions per clock cycle. In order to execute multiple instructions per clock cycle, multiple independent functional units that can execute concurrently are required.
The overlap of the fetching and decoding of one instruction with the execution of a second instruction is called pipelining. In pipelined superscalar data processing systems, care must be taken to avoid dependencies where multiple instructions are fetched, decoded, and executed in a single cycle.
There are three types of data dependencies. A read after write hazard occurs when an instruction tries to read a source before a previous instruction writes the source. A write after read hazard occurs when an instruction tries to write a destination before a previous instruction reads it. A write after write hazard occurs when an instruction writes a destination before a previous instruction writes it.
One solution to solving the dependence problem is to rename the logical registers associated with the instructions. By renaming the logical registers, each instruction within the cycle can be executed concurrently and correctly. A problem arises, however, when an instruction is a conditional branch instruction. Register renaming is a mechanism for dealing with these dependencies in a processor which executes instructions out-of-order. The target register associated with each instruction is renamed to a unique physical register. Thereby, the instructions may execute properly concurrently, and out-of-order.
A condition branch instruction is an instruction which specifies a conditional branch and the conditions that have to be satisfied for the conditional branch to occur. In order to speed execution of instructions, for each conditional branch, a prediction is made regarding whether the conditions will occur which will cause the branch. This prediction is made during the cycle during which the conditional branch is decoded, and prior to completing the execution of each conditional branch. In the event a conditional branch is predicted incorrectly, the state of all registers affected by the conditional branch must be restored to their states which existed just prior to encountering the conditional branch. Upon completion of execution of the instruction, if the branch instruction was correctly predicted, the stored register values are discarded.
Therefore a need exists for a method and system in a superscalar data processing system to permit concurrent processing of a plurality of instructions of a particular type within a single clock cycle.